Multi-chip module system

ABSTRACT

Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.

This is a division of application Ser. No. 08/614,301, filed Mar. 12,1996, now U.S. Pat. No. 5,807,762.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to multi-chip module systems and theirmethod of fabrication. More specifically, the present invention relatesto multi-chip module systems and their method of fabrication usingknown-good-die (KGD) therein.

2. State of the Art

An integrated circuit (IC) typically includes a semiconductor die (die)electrically attached to a leadframe, which provides physical supportfor the die and is used to connect the die with external circuitrylocated on a substrate. In such an arrangement, the leadframe and dieare typically connected by means of wires, such as gold, aluminum, etc.,being encapsulated within a plastic package, although ceramic and metalpackages may also be used depending on the operating environment and thepackaging requirements of the die.

With ever increasing demands for miniaturization and higher operatingspeeds, multi-chip module systems (MCM's) are increasingly attractive ina variety of electronics. MCM's, which contain more than one die, canhelp minimize the system operational speed restrictions imposed by longprinted circuit board connection traces by combining, for example, theprocessor, memory, and associated logic into a single package. Inaddition, MCM's offer packaging efficiency.

Generally, MCM's may be designed to include more than one type of diewithin a single package, or may include multiples of the same die, suchas the single in-line memory module (SIMM) or single in-line package(SIP).

It is well known that semiconductor dies have an early failure rate,often referred to in reliability terms as infant mortality. As with allassemblies, this phenomenon is also present in MCM's. For example, anMCM composed of ten dice, each die having an individual reliabilityyield of 95%, would result in a first pass test yield of less than 60%,while an MCM composed of twenty dice, each die having an individualreliability yield of 95%, would produce a first pass test yield of lessthan 36%. The market's perception of this phenomenon affects thedecision to use MCM's in various applications.

Previously, an unacceptable die in an MCM, which has been subjected toburn-in and testing, has required either the replacement of such a dieor the discard of the MCM. Both being time consuming and expensive.Additionally, since replacing an unacceptable die on an MCM poses risksto other MCM components during the replacement operation, it may bedesirable to discard an MCM with such a die, rather than attempt reworkthe MCM, particularly where the reliability of the replacement die isnot known.

Depending on the extent of testing and/or burn-in procedures employed, adie may typically be classified into varying levels of reliability andquality. For example, a die may meet only minimal quality standards byundergoing standard probe testing or ground testing while still in waferform, while an individual separated die may be subjected to tests atfull-range temperatures with full burn-in being subsequently termed aknown-good-die (KGD).

A cost-effective method for producing known reliable MCM's is desirablefor industry acceptance and use of MCM's in various applications. In anattempt to provide known reliable MCM's complying with consumerrequirements, it is desirable either to fabricate an MCM of KGD or tofabricate an MCM of probe tested dice and subsequently subject the MCMto burn-in and performance testing. However, using only KGD in an MCMmay not be cost effective since each KGD has been subjected toperformance and burn-in testing, which are costly. In contrast to theuse of all KGD in an MCM, when using die with well known production andreliability histories, particularly where the die being used is known tohave a low infant mortality rate, the use of such minimally tested dieto produce an MCM may be the most cost effective alternative.

As previously stated, since typical testing and burn-in procedures aregenerally labor and time intensive posing significant risks to the diceof an MCM, in an instance where an MCM is produced from minimally testeddie, in the event that MCM contains an unacceptable die, replacement ofunacceptable die with a KGD is preferable in the rework of the MCMbecause rework with KGD should not require the MCM to be subjected tofurther burn-in, but rather, only performance testing.

An example of a multi-chip module having a plurality of dynamic randomaccess memory devices (DRAM's) used as memory in a computer isillustrated in U.S. Pat. No. 4,992,850, issued Feb. 12, 1991, to Corbettet al., assigned to the assignee of the present invention.

An example of a method and apparatus for the testing and burn-in of anindividual die prior to packaging is illustrated in U.S. Pat. No.5,424,652, issued Jun. 13, 1995, to Hembree et al., assigned to theassignee of the present invention. Such a method and apparatus provide asource of KGD to allow for the rework of an unacceptable die in an MCMwith a KGD.

Other examples of a method for the testing and burn-in of an individualdie prior to packaging are illustrated in U.S. Pat. No. 5,448,165 and5,475,317.

In other instances, it is known to test a die in a package forfunctionality and replace any defective die. Such is illustrated in U.S.Pat. Nos. 5,137,836, 5,378,981, and 5,468,655.

In yet another instance, as illustrated in U.S. Pat. No. 5,239,747 and5,461,544, it is known to test a multi-chip module (SIMM) to determineif any of the semiconductor devices mounted thereon are non-functionaland, if so, replace the defective device with a device which has eitherbeen subjected to burn-in, or the entire multi-chip module can besubjected to another burn-in process after the replacement of thedefective device. However, the defective devices are merely replaced byremoving the defective device and replacing it with another, either adevice subjected to burn-in or not. This process can be complicated,time consuming and costly depending upon the type of device, the type ofmounting of the device on the substrate, and the type of substrate usedfor mounting.

Therefore, a need exists for the cost-efficient fabrication of MCM's ofknown performance and reliability requirements.

SUMMARY

The present invention relates to known reliable multi-chip modulesystems and their method of fabrication. The present invention relatesto multi-chip module systems and their method of fabrication usingknown-good-die (KGD) therein. In one embodiment of the presentinvention, a multi-chip module system is fabricated from probe testeddie, burned-in, and if a die requires replacement after burn-in of themulti-chip module system, a known-good-die is used for replacement ofthe failed die. In another embodiment of the present invention, themulti-chip module system and the method of fabrication thereof includesa module having the capacity to accommodate at least two semiconductordice, the module accommodating at least one more die than is desired tomeet the module's intended function and performance parameters.Accordingly, the multi-chip module of the present invention includes atleast one die and at least one vacant position capable of accommodatingone or more additional dice where an acceptable die may be located inthe module if it is determined that an unacceptable die is present fromthe testing and/or burn-in of the multi-chip module system.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the present invention can be more readilyunderstood with reference to the following description and appendedclaims when taken in conjunction with the accompanying drawings wherein:

FIG. 1 is a top view of one embodiment of a SIMM type MCM in accordancewith the present invention;

FIG. 2 is a top view of the corrected SIMM of FIG. 1, illustrating theaddition of a KGD;

FIG. 3 is a top view of one embodiment of an MCM illustrating differenttypes of dice and two different vacant die positions;

FIG. 4 is a top view of an alternative embodiment of the MCM of FIG. 3,having a single vacant die position for the accommodation of a dieadapter;

FIG. 5 is a top view of one embodiment of a semiconductor die adapter inaccordance with the present invention;

FIG. 6 is a top view of an alternative embodiment of a semiconductor dieadapter; and

FIG. 7 is a top view of another alternative embodiment of asemiconductor die adapter illustrating the accommodation of multipledice.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

In accordance with the method of the present invention, a multi-chipmodule system (MCM) having at least one die attached thereto issubjected to burn-in procedures and performance testing to identifywhether any die or dice of the MCM is unacceptable. Such proceduresbeing well known in the art.

In the event that one or more dice is unacceptable, a known-good-die(KGD) compatible with the unacceptable die is added to the MCM bypositioning the KGD into a vacant position on the MCM which position isconfigured to accept such a die as the unacceptable die. Likewise, wherean MCM contains more than one unacceptable die, an equal number of KGD'smay be added into vacant positions on the MCM which positions have beenconfigured to accept such dice as the unacceptable dice. It is to beunderstood, however, that fewer KGD's may be added than there areunacceptable dice where the combined effect of the KGD added to the MCMproduces the same desired result. For example, where a ten-megabytememory MCM having ten individual one-megabyte dice is determined to havetwo unacceptable dice, a single two-megabyte die may be added to the MCMfor an equivalent overall result of ten-megabytes of memory.

The method of the present invention is applicable to MCM's which containonly one type of die, as well as to MCM's which contain more than onetype of die. In the situation where an MCM contains only one type of die(e.g., SIMM type or SIP type), one or more vacant positions are providedon the MCM to accommodate an additional die in the event the MCM failsto meet its pre-determined performance characteristics. The vacantposition or positions are constructed with the necessary connections andtraces in the event a KGD is later added to the MCM.

In one embodiment, a SIMM having ten individual dice, for example, wouldbe constructed with eleven die positions, wherein the eleventh positionwould be left vacant. Although the eleventh position is initially leftvacant, appropriate connections are provided in the SIMM in case a dieis subsequently positioned in the vacant slot. In the event one die isfound to be unacceptable, a KGD would be added to the eleventh positionand, if possible, the unacceptable die and the associated circuitry onthe SIMM disabled and would be left on the SIMM. Accordingly, theunacceptable die may not need to be removed and no further burn-in isrequired since the added die is a KGD, thereby saving considerableexpense and time and avoiding damage or complications associated withany further burn-in of the SIMM after the replacement of theunacceptable die. The corrected SIMM, including both the unacceptabledie and the added KGD, then only needs to be subjected to testingprocedures to ensure proper functioning of the SIMM. However, suchtesting is inexpensive and not time consuming when compared to eitherburn-in procedures or burn-in and subsequent testing procedures.Alternatively, if the unacceptable die cannot be disabled and remain inthe SIMM, the unacceptable die is removed from its location or merelydisconnected while functionally leaving the die in its place and a KGDadded in the vacant position in the SIMM as described hereinbefore.

Particularly in situations where an MCM contains more than one type ofdie, a variety of different vacant positions may be provided atappropriate positions on the MCM so as to maximize efficient use ofspace on the MCM. In addition, a variety of adapters may be used forattaching different types of dice to an MCM. Different adapters, eachbeing positionable within the same vacant slot of an MCM, are capable ofsupporting different types of dice. In particular circumstances, morethan one type of die may be supported by a single adapter. In oneembodiment, the adapter may also serve as a testing substrate therebyfacilitating individual die burn-in, wherein the die is attached to theadapter prior to burn-in.

As will be seen from the description of the present invention describedhereinbelow the method of the present invention facilitates thefabrication of known reliability multi-chip modules (MCM) and reducesthe time and costs associated with the fabrication thereof.

Referring to the FIG. 1 of the drawings, a SIMM type MCM 10 inaccordance with the present invention is shown. The SIMM 10 has eightdice 12 of the same type mounted on a suitable substrate 11. Althoughthe SIMM 10 requires eight dice 12 to meet its design requirements, aninth die position 14 is produced on substrate 11 of the SIMM 10 withsuitable connections (not shown). The SIMM 10, having eight dice 12 andone vacant position 14 is subjected to suitable predetermined testingand burn-in procedures to ensure conformance with desired predeterminedperformance characteristics.

Referring to FIG. 2 of the drawings, in the event the SIMM 10 fails tomeet its predetermined performance characteristics, if possible, theidentified unacceptable die 12', determined through procedures wellknown in the art, is not reworked, but is instead left in its respectiveposition on the SIMM 10 with the die and its associated circuitry on theSIMM being disabled. As shown, an individual KGD die 16, determinedthrough procedures well known in the art, is added to the substrate 11of SIMM 10 in the vacant position 14. The resulting corrected SIMM 20,after being subject to appropriate testing to verify its performancecharacteristics, is then known to be a reliable MCM without requiringadditional burn-in. Alternatively, if the unacceptable die 12' may notremain in the SIMM 10, it is removed and a KGD is added to the substrate11 of the SIMM 10 in the vacant position 14 as described hereinbefore.

It is to be understood that in the event two dice of the SIMM have beenfound to be unacceptable, a single KGD 16, having twice the memory ofeach of the individual dice 12, may be installed in the vacant position14. An MCM having more than two failed dice can likewise be corrected inthe same manner. In alternative embodiments, particularly where size andspace limitations are not critical, more than one vacant position 14 maybe produced on the SIMM 10, whereby the number of unacceptable dice 12'may be replaced by an equivalent number of KGD's 16.

Referring to FIG. 3, a first MCM 30 having more than one type of die isshown. In one embodiment, two different vacant positions 32 and 34 areproduced on the substrate 31 of the first MCM 30, each capable ofaccommodating different types of dice. Suitable electrical connectionsare provided to the vacant positions 32 and 34 on the substrate 31 inthe event a die is to be subsequently added to either of the vacantpositions 32 or 34. The first MCM 30 of FIG. 3 is designed with threedifferent types of dice 40, 42, and 44. In the event that die 40 isunacceptable, an equivalent KGD (not shown) may be added to the vacantposition 32. Likewise, in the event that die 42 is unacceptable, anequivalent KGD may be added to the vacant position 34. In thisparticular example, an equivalent of die 44, if determined to beunacceptable, is generally not possible due perhaps to the relativelylarge size of the die 44 and the fact that there is only one die 44 onthe first MCM 30. However, under certain circumstances, the first MCM30, having an unacceptable die 44, may be corrected by adding acombination of KGD's equivalent to dice 40 and 42 in vacant positions 32and 34, respectively. An alternative vacant position (not shown) may beprovided to accommodate a KGD equivalent of die 44. Additionally, thevacant positions 32 and 34 may be located on opposite sides of thesubstrate 31 of the MCM 30, if desired.

It is to be understood that any appropriate number of vacant positions32 and 34 may be provided on the substrate 31 of the first MCM 30. Inalternative embodiments, at least one vacant position is provided foreach type of die utilized on an MCM. In another embodiment of theinvention, the vacant position 32 is positioned within the regiondefined by the larger vacant position 34. More than one such "doublevacancy" position may be produced on a single MCM.

Referring to FIG. 4, an alternative embodiment of the first MCM 30 isshown generally at 60. The second MCM 60 is designed to meet the sameconsumer operational and performance requirements as those of the firstMCM 30, and contains the same number and types of dice 40, 42, and 44.However, the substrate 61 of the second MCM 60 contains an adaptervacancy 62. The adapter vacancy 62 is designed to accommodate a firstadapter 64 or a second adapter 66, as shown in FIGS. 5 and 6,respectively. The first adapter 64 is designed to accommodate anequivalent of the individual die 40, while the second adapter 66 isdesigned to accommodate an equivalent of the individual die 42. Theadapters have the same footprints, thereby being positionable within thesame type of slots, and utilize the electrical connections of thesubstrate 61 of the second MCM 60, while allowing for the accommodationof different types of dice. The use of one type of adapter in accordancewith the present invention is described in co-pending application forFlip Chip Adapter Package for Bare Die, Ser. No. 08/574,662, filed Dec.19, 1995, which is hereby incorporated herein by reference.

Referring to FIG. 5, the adapter 64 includes a die slot 70 andelectrical connectors 72. Different adapters may contain differentelectrical connections. In one embodiment, a single adapter is capableof accommodating two different types of dice, and the orientation of theadapter onto the MCM is determined by the type of die utilized with theadapter, so as to utilize the appropriate electrical connections of theMCM. For example, an adapter accommodating one type of die is positionedon an MCM at one orientation, while another adapter accommodating adifferent type of die may be positioned on the MCM at an orientationrotated 90° with respect to the adapter accommodating the first type ofdie.

In accordance with the present invention, a second MCM 60 having anunacceptable die 40 or 42 may be corrected by adding the appropriateadapter 64 or 66 to the adapter vacancy 62 of the substrate 61. Inalternative embodiments, a multiple adapter 80, as shown in FIG. 7, mayaccommodate more than one die including different types and sizes ofdie.

In one embodiment, the adapter to be positioned within the adaptervacancy 62 is used as a substrate for the testing and burn-in of anindividual die. Accordingly, an unacceptable individual die and itscorresponding adapter are dispensed with relatively inexpensively, whilea KGD previously attached to an adapter is ready to be added to theadapter vacancy of an MCM.

As previously stated, one vacant position on a substrate can bepositioned within the region defined by the position accommodatingdifferent die types and sizes while consuming a minimum of space on theadapter.

Characteristics of the described and illustrated embodiments areintended for illustrative purposes, and are not to be consideredlimiting or restrictive. It is to be understood that various adaptationsand modifications may be made to the embodiments illustrated hereinwithout departing from the spirit and scope of the invention, as definedby the following claims and equivalents thereof.

What is claimed is:
 1. A single-in-line multi-chip memory module systemcomprising:a substrate having at least a first position having, in turn,a predetermined configuration for locating a first semiconductor devicethereat and having at least one other vacant position having, in turn, apredetermined configuration for locating a second semiconductor devicethereat on the single-in-line multi-chip memory module system; and afirst semiconductor device located in the first position of thesubstrate for use in said single-in-line multi-chip memory modulesystem, the first semiconductor device having a first predeterminedperformance characteristic.
 2. The single-in-line multi-chip memorymodule system of claim 1, further comprising:the at least one othervacant position having a predetermined configuration for locating asecond semiconductor device thereat which is substantially the same asthe first semiconductor device.
 3. The single-in-line multi-chip memorymodule system of claim 1, further comprising:the at least one othervacant position having a predetermined configuration for locating asecond semiconductor device thereat; and a second semiconductor devicehaving a predetermined performance characteristic substantially equal tothat of the first predetermined performance characteristic of the firstsemiconductor device.
 4. The single-in-line multi-chip memory modulesystem of claim 1, further comprising:the at least one other vacantposition having a predetermined configuration for locating a secondsemiconductor device thereat; and a second semiconductor device having apredetermined performance characteristic of at least substantially twicethat of the first predetermined performance characteristic of the firstsemiconductor device.
 5. A single-in-line multi-chip memory modulesystem comprising:a substrate having a first position having, in turn, apredetermined configuration for locating a first semiconductor devicethereat, having a second position having, in turn, a predeterminedconfiguration for locating a second semiconductor device thereat, andhaving at least one other vacant position having, in turn, apredetermined configuration for locating a third semiconductor devicethereat on the single-in-line multi-chip memory module system; a firstsemiconductor device located in the first position of the substrate foruse in said single-in-line multi-chip memory module system, the firstsemiconductor device having a first predetermined performancecharacteristic; and a second semiconductor device located in the secondposition of the substrate for use in said single-in-line multi-chipmemory module system, the second semiconductor device having a secondpredetermined performance characteristic.
 6. The single-in-linemulti-chip memory module system of claim 5, further comprising:the atleast one other vacant position having a predetermined configuration forlocating a third semiconductor device thereat which is substantially thesame as the first semiconductor device.
 7. The single-in-line multi-chipmemory module system of claim 5, further comprising:the at least oneother vacant position having a predetermined configuration for locatinga third semiconductor device thereat; and a third semiconductor devicehaving a predetermined performance characteristic substantially equal tothat of the first predetermined performance characteristic of the firstsemiconductor device.
 8. The single-in-line multi-chip memory modulesystem of claim 5, further comprising:the at least one other vacantposition having a predetermined configuration for locating a thirdsemiconductor device thereat; and a third semiconductor device having apredetermined performance characteristic of at least substantially twiceto that of the first predetermined performance characteristic of thefirst semiconductor device.
 9. The single-in-line multi-chip memorymodule system of claim 5, further comprising:the at least one othervacant position having a predetermined configuration for locating athird semiconductor device thereat; and a third semiconductor devicehaving a predetermined performance characteristic of at leastsubstantially twice to that of the second predetermined performancecharacteristic of the second semiconductor device.
 10. Thesingle-in-line multi-chip memory module system of claim 5, furthercomprising:the at least one other vacant position having a predeterminedconfiguration for locating a third semiconductor device thereat; and athird semiconductor device having a predetermined performancecharacteristic of at least substantially twice that of the first andsecond predetermined performance characteristics of the firstsemiconductor device and the second semiconductor device combined. 11.The single-in-line multi-chip memory module system of claim 5, whereinthe first semiconductor device comprises a memory device.
 12. Thesingle-in-line multi-chip memory module system of claim 5, wherein thesecond semiconductor device comprises a memory device.
 13. Thesingle-in-line multi-chip memory module system of claim 5, wherein thefirst semiconductor device comprises a microprocessor device.
 14. Thesingle-in-line multi-chip memory module system of claim 5, wherein thesecond semiconductor device comprises a microprocessor device.
 15. Thesingle-in-line multi-chip memory module of claim 7, further comprising:athird semiconductor device; and an adapter connected to the thirdsemiconductor device, the adapter having a configuration for connectingthe adapter to the at least one other vacant position on the substrateto connect the third semiconductor device to the substrate.
 16. Asingle-in-line multi-chip memory module system comprising:a substratehaving a first position having, in turn, a predetermined configurationfor locating a first semiconductor device thereat, having a secondposition having, in turn, a predetermined configuration for locating asecond semiconductor device thereat, having a first vacant positionhaving, in turn, a predetermined configuration for locating a thirdsemiconductor device thereat, and having a second vacant positionhaving, in turn, a predetermined configuration for locating a fourthsemiconductor device thereat on the single-in-line multi-chip memorymodule; a first semiconductor device located in the first position ofthe substrate for use in said single-in-line multi-chip memory modulesystem, the first semiconductor device having a first predeterminedperformance characteristic; and a second semiconductor device located inthe second position of the substrate for use in said single-in-linemulti-chip memory module system, the second semiconductor device havinga second predetermined performance characteristic.
 17. Thesingle-in-line multi-chip memory module of claim 16, wherein:the firstvacant position located on the substrate is located on one side of thesubstrate; and the second vacant position located on the substrate islocated on another side of the substrate.
 18. A multi-chip module systemhaving a plurality of types of semiconductor devices located thereincomprising:a substrate having at least a first position having, in turn,a predetermined configuration for locating a first type semiconductordevice thereat and having at least one other vacant position having, inturn, a predetermined configuration for locating a second typesemiconductor device thereat on the multi-chip module system, the secondtype semiconductor device being substantially different type than thefirst type semiconductor device; and a first type semiconductor devicelocated in the first position of the substrate for use in saidmulti-chip module system, the first type semiconductor device having afirst predetermined performance characteristic.
 19. The multi-chipmodule system of claim 18, further comprising:the at least one othervacant position having a predetermined configuration for locating asecond type semiconductor device thereat, the second type semiconductordevice being substantially different than the first type ofsemiconductor device.
 20. The multi-chip module system of claim 18,further comprising:the at least one other vacant position having apredetermined configuration for locating a second type semiconductordevice thereat, the second type semiconductor device being substantiallydifferent than the first type semiconductor device; and a secondsemiconductor device having a predetermined performance characteristicsubstantially equal to that of the first predetermined performancecharacteristic of the first type semiconductor device.
 21. Themulti-chip module system of claim 18, further comprising:the at leastone other vacant position having a predetermined configuration forlocating a second type semiconductor device thereat, the second typesemiconductor device being substantially different than the first typesemiconductor device; and a second semiconductor device having apredetermined performance characteristic of at least substantially twicethat of the first predetermined performance characteristic of the firsttype semiconductor device.
 22. A multi-chip module system having aplurality of types of semiconductor devices located therein comprising:asubstrate having a first position having, in turn, a predeterminedconfiguration for locating a first type semiconductor device thereat,having a second position having, in turn, a predetermined configurationfor locating a second type semiconductor device thereat, the second typesemiconductor device substantially different than the first typesemiconductor device, and having at least one other vacant positionhaving, in turn, a predetermined configuration for locating a third typesemiconductor device thereat on the multi-chip module system, the thirdtype semiconductor device being one of the first type semiconductordevice and the second type semiconductor device; a first typesemiconductor device located in the first position of the substrate foruse in said multi-chip module system, the first type semiconductordevice having a first predetermined performance characteristic; and asecond type semiconductor device located in the second position of thesubstrate for use in said multi-chip module system, the second typesemiconductor device having a second predetermined performancecharacteristic.
 23. The multi-chip module system of claim 22, furthercomprising:the at least one other vacant position having a predeterminedconfiguration for locating a third type semiconductor device thereatwhich is substantially the same as the first type semiconductor device.24. The multi-chip module system of claim 22, further comprising:the atleast one other vacant position having a predetermined configuration forlocating a third type semiconductor device thereat; and a third typesemiconductor device having a predetermined performance characteristicsubstantially to that of the first predetermined performancecharacteristic of the first type semiconductor device.
 25. Themulti-chip module system of claim 22, further comprising:the at leastone other vacant position having a predetermined configuration forlocating a third type semiconductor device thereat; and a third typesemiconductor device having a predetermined performance characteristicof at least substantially twice to that of the first predeterminedperformance characteristic of the first type semiconductor device. 26.The multi-chip module system of claim 24, further comprising:an adapterconnected to the third type semiconductor device, the adapter having aconfiguration for connecting the adapter to the at least one othervacant position on the substrate to connect the third type semiconductordevice to the substrate.
 27. A multi-chip module system having aplurality of types of semiconductor devices located therein comprising:asubstrate having a first position having, in turn, a predeterminedconfiguration for locating a first type semiconductor device thereat,having a second position having, in turn, a predetermined configurationfor locating a second type semiconductor device thereat, the second typesemiconductor device substantially different than the first typesemiconductor device, having a first vacant position having, in turn, apredetermined configuration for locating a third type semiconductordevice thereat, the third type semiconductor device being one of thefirst type semiconductor device and the second type semiconductordevice, and having a second vacant position having, in turn, apredetermined configuration for locating a fourth type semiconductordevice thereat on the multi-chip module, the fourth type semiconductordevice being one of the first type semiconductor device and the secondtype semiconductor device; a first type semiconductor device located inthe first position of the substrate for use in said multi-chip modulesystem, the first type semiconductor device having a first predeterminedperformance characteristic; and a second type semiconductor devicelocated in the second position of the substrate for use in saidmulti-chip module system, the second type semiconductor device having asecond predetermined performance characteristic.
 28. The multi-chipmodule of claim 27, wherein:the first vacant position located on thesubstrate is located on one side of the substrate; and the second vacantposition located on the substrate is located on another side of thesubstrate.